中古 NEXTEST / TERADYNE Magnum SSV #9071674 を販売中
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ID: 9071674
Tester
Max board: 20
Total channels: 2560
Sub-site A channel: 1280
Sub-site B channel: 1280
Site controller: 20
Configuration:
HSB1
Loading TCAL Data on t_hsb1, t_pe32_1
Loading TCAL Data on t_hsb1, t_pe32_2
Loading TCAL Data on t_hsb1, t_pe32_3
Loading TCAL Data on t_hsb1, t_pe32_4
Loading VCAL Data on t_hsb1, t_pe32_1
Loading VCAL Data on t_hsb1, t_pe32_2
Loading VCAL Data on t_hsb1, t_pe32_3
Loading VCAL Data on t_hsb1, t_pe32_4
Loading VCAL Data on t_hsb1, t_dps_pmu_1
Loading VCAL Data on t_hsb1, t_dps_pmu_2
Loading VCAL Data on t_hsb1, t_dps_pmu_3
Loading VCAL Data on t_hsb1, t_dps_pmu_4
Adjusting TimingCal data for t_hsb1: revision 16 to 21
active dut = 0
The test program is loaded
TestStarted(1)...
Started: 07/17/14 17:14:11
Site 20 ( Chassis 4, Slot 5 )
Board PWB PWB PWA PWA LVM DBM ECR1 ECR2 X Y D
Name Number Rev Number Rev SDR/DDR MBits MBits MBits bits bits bits
------------------------------------------------------------------------------------------------------
HSBX 2 507487 1 0 (0) 576 (2) 2304(2) 2304(2) 18* 16* 36*
PEX_1 507466 1 507467 3
PEX_2 507466 1 507467 3
PEX_3 507466 1 507467 3
PEX_4 507466 1 507467 3
DP_1 504582 4 504583 9
DP_2 504582 4 504583 9
DP_3 504582 4 504583 9
DP_4 504582 4 504583 9
IPC 505306 5 505305 17 Firmware Revision : 3.6.2
* NOTE: The ECR X, Y, D bits represent the maximum allowable configuration.
- Revision Codes for Dimms -
DIMM Base PWA PWA LVM DBM ECR
Name Number Number Rev MVec MBits MBits
---------------------------------------------------------------------
DBM-DIMM1 505479 505942 1 288
DBM-DIMM2 505479 505942 1 288
ECR1-DIMM1 505480 505938 1 1152
ECR1-DIMM2 505480 505938 1 1152
ECR2-DIMM1 505480 505938 1 1152
ECR2-DIMM2 505480 505938 1 1152
- Revision Codes for FPGAs -
FPGA SW HW
Name Rev Rev
-------------------------
CPUI Fpga 0x1 0x1
TG1 Fpga 0x1 0x15
TG2 Fpga 0x1 0x15
TG3 Fpga 0x1 0x15
TG4 Fpga 0x1 0x15
TG5 Fpga 0x1 0x15
TG6 Fpga 0x1 0x15
TG7 Fpga 0x1 0x15
TG8 Fpga 0x1 0x15
APG1 Fpga 0x1 0xea
APG2 Fpga 0x1 0xae
DBM1 Fpga 0x1 0xae
PSLE1 Fpga 0x1 0x88
PSS1 Fpga 0x1 0x90
PSLE2 Fpga 0x1 0x88
PSS2 Fpga 0x1 0x90
PSLE3 Fpga 0x1 0x88
PSS3 Fpga 0x1 0x90
PSLE4 Fpga 0x1 0x88
PSS4 Fpga 0x1 0x90
LVM1 Fpga 0x1 0x36
LVM2 Fpga 0x1 0x36
ECR1 Fpga 0x1 0xbb
ECR2 Fpga 0x1 0xbc
Nextest software release: C:\nextest\h2.0.12\Bin\Ui.exe
Running on MAGNUM_X20 system# 844071
Testing APG read,write registers via cpu [apg_rw_regs_tb]
Testing Address registers and LBDATA
Testing MAR and INTA
Testing JAM, DMAIN, DBASE, YINDEX
Testing Unique values
Testing APG counter RAM - short march [apg_counter_ram_short_march_tb]
Testing APG reload RAM - short march [apg_reload_ram_short_march_tb]
Testing APG XDTOPO RAM - short march [apg_xdtopo_ram_short_march_tb]
Testing APG YDTOPO RAM - short march [apg_ydtopo_ram_short_march_tb]
Testing APG uRAM - short march [apg_uram_ram_short_march_tb]
Testing APG Cycle Length RAM - short march [apg_cycle_ram_short_march_tb]
Testing APG DAC RAM - short march [apg_dac_ram_short_march_tb]
Testing APG XTOPO RAM - short march [apg_xtopo_ram_short_march_tb]
Testing APG YTOPO RAM - short march [apg_ytopo_ram_short_march_tb]
Testing APG User RAM - short march [apg_user_ram_short_march_tb]
Testing APG vRAM - short march [apg_vram_ram_short_march_tb]
VMC1 No vector memory installed - skipping test
Testing HSB 100Mhz clock frequency [hsb_clk_check_tb]
Testing APG counter functions [apg_counter_tests_tb]
Pattern start is at 3e7
Testing Counter loading
Testing Counter address
Testing Reload loading
Testing Reload address
Testing Reload counters from reload registers
Testing Counter DECR
Testing Counter INCR
Testing Counter DECR2
Testing MAR increments, stack nesting [apg_mar_and_stack_tests_tb]
Testing MAR increments
Testing Stack nesting, 1st pass
Testing Stack nesting, 2nd pass
Stack nesting, 50nS
Stack nesting, 20nS
Testing APG counter branching [apg_counter_branching_tb]
Pattern start is at 4fd
Testing APG timer branching and accuracy [apg_timer_branching_tb]
Pattern start is at b1
Testing APG interrupt branch logic and addressing [apg_interrupt_branching_tb]
Pattern start is at 5fb
Testing APG address generators [apg_address_generators_tb]
Pattern start is at 50c
Testing uDATA loads
Testing COMP function
Testing logic functions
Testing add
Testing subtract
Testing decrement and increment
Testing Y to X carries and borrows
Testing X to Y carries and borrows
Testing APG data generator [apg_data_generator_tb]
Pattern start is at 5d
Testing uDATA loads
Testing Count up and down with shift left, 18 bit DMAIN register
Testing Count up and down with shift left, 18 bit DBASE register
Testing Shift right, 18 bit DMAIN register
Testing Shift right, 18 bit DBASE register
Testing Rotate left, 18 bit DMAIN register
Testing Rotate right, 18 bit DMAIN register
Testing Rotate left, 18 bit DBASE register
Testing Rotate right, 18 bit DBASE register
Testing Rotate left, 36 bit DMAIN register
Testing Rotate right, 36 bit DMAIN register
Testing Rotate left, 36 bit DBASE register
Testing Rotate right, 36 bit DBASE register
Testing Shift left, 36 bit DMAIN register
Testing Shift left, 36 bit DBASE register
Testing Shift right, 36 bit DMAIN register
Testing Shift right, 36 bit register
Testing APG error pipelines [apg_error_pipe_tb]
Testing APG data inversions [apg_data_inversions_tb]
Checking bit1 functions
Bit1 as Y Address Bits PASSED
Bit1 as X Address Bits PASSED
Checking bit2 functions
Bit2 as Y Address Bits PASSED
Bit2 as X Address Bits PASSED
Checking bit1, bit2 logical combinations
Bit1 AND Bit2 PASSED
Bit1 OR Bit2 PASSED
Bit1 XOR Bit2 PASSED
Check X and Y parity
XYodd PASSED
XYEven PASSED
Xeven_Yodd PASSED
Xodd_Yeven PASSED
Xodd PASSED
Xeven PASSED
Yodd PASSED
Yeven PASSED
Check DTOPO inversions
DTopo RAM PASSED
Check Yindex Counter
YIndex Counter PASSED
Check Yindex Mask Inversions
yindex plus Y, yindex = 0xffff
yindex plus Y bar, yindex = 0xffff
yindex plus Y, Y = 0xffff
yindex plus Y bar, Y = 0x0000
YIndex Mask Inversions PASSED
Check XY Equality Functions
xmain equal to xbase (XEQB)
xmain less than xbase (XLTB)
xmain less than or equal to xbase (XLEB)
xmain equal to xfield or xbase (XEQBORF)
ymain equal to ybase (YEQB)
ymain less than ybase (YLTB)
ymain less than or equal to ybase (YLEB)
ymain equal to yfield or ybase (YEQBORF)
xymain equal to xybase (XYEQB)
xymain less than xybase (XYLTBXF)
xymain less than xybase (XYLTBYF)
xymain less than or equal to xybase (XYLEBXF)
xymain less than or equal to xybase (XYLEBYF)
inversion from uRAM (INVSNS)
inversion from uDATA (XORINV)
Testing ECR X Scramble RAM - short march [ecr_xscram_short_march_tb]
Testing ECR Y Scramble RAM - short march [ecr_yscram_short_march_tb]
Testing ECR Row RAM - short march [ecr_rowram_short_march_tb]
Testing ECR Col RAM - short march [ecr_colram_short_march_tb]
Testing ECR dimm bit independence [ecr_dimm_bit_independence_tb]
Testing ECR 5N March [ecr_dimm_hw_long_march_tb]
Testing DBM DRAM - short march [dbm_dimm_short_march_tb]
Testing DBM DIMM 5N March [dbm_dimm_hw_5N_march_tb]
Testing TG Pin Scramble RAM - short march [tg_psram_short_march_tb]
Testing TG timing RAM - short march [tg_timing_ram_short_march_tb]
Testing TG SLVM RAM - short march [tg_slvm_ram_short_march_tb]
Testing TG broadcast mode [tg_broadcast_tb]
Testing TG to PE communications [tg_pe_communication_tb]
Testing PE error generation [pe_error_gen_tb]
Testing PE force drive state [pe_force_drive_state_tb]
Testing Pin Scramble Format RAM - short march [format_ram_short_march_tb]
Testing Pin Scramble RAM - short march [pe_psram_short_march_tb]
Testing DP ADC [adc_tb]
Testing DP PMU voltage force [pmu_vf_tb]
Testing DP 1 PMU voltage force DACs
Testing DP 1 PMU voltage force level accuracy
Testing DP 2 PMU voltage force DACs
Testing DP 2 PMU voltage force level accuracy
Testing DP 3 PMU voltage force DACs
Testing DP 3 PMU voltage force level accuracy
Testing DP 4 PMU voltage force DACs
Testing DP 4 PMU voltage force level accuracy
Testing DP PMU current force [pmu_if_tb]
Testing DP 1 PMU current force DACs
Testing DP 1 PMU current force level accuracy
Testing DP 2 PMU current force DACs
Testing DP 2 PMU current force level accuracy
Testing DP 3 PMU current force DACs
Testing DP 3 PMU current force level accuracy
Testing DP 4 PMU current force DACs
Testing DP 4 PMU current force level accuracy
Testing DP DPS voltage force [dps_vf_tb]
Testing DP 1 DPSn DACs
Testing DP 1 DPSn level accuracy
Testing DP 1 DPSn apg level DAC select path
Testing DP 1 DPSa DACs
Testing DP 1 DPSa level accuracy
Testing DP 2 DPSn DACs
Testing DP 2 DPSn level accuracy
Testing DP 2 DPSn apg level DAC select path
Testing DP 2 DPSa DACs
Testing DP 2 DPSa level accuracy
Testing DP 3 DPSn DACs
Testing DP 3 DPSn level accuracy
Testing DP 3 DPSn apg level DAC select path
Testing DP 3 DPSa DACs
Testing DP 3 DPSa level accuracy
Testing DP 4 DPSn DACs
Testing DP 4 DPSn level accuracy
Testing DP 4 DPSn apg level DAC select path
Testing DP 4 DPSa DACs
Testing DP 4 DPSa level accuracy
Testing DP PMU/DPS current measure [range_resistor_tb]
Testing DP PMU comparators [pmu_comp_tb]
Testing DP 1 PMU comparator DACs
Testing DP 1 PMU comparator accuracy
Testing DP 2 PMU comparator DACs
Testing DP 2 PMU comparator accuracy
Testing DP 3 PMU comparator DACs
Testing DP 3 PMU comparator accuracy
Testing DP 4 PMU comparator DACs
Testing DP 4 PMU comparator accuracy
Testing PE32 PMU leakage current [pmu_leakage_tb]
Testing PE32 VIHH pin level [vihh_tb]
Testing VIHH DACs
Testing VIHH level accuracy
Testing VIHH apg level DAC select path
Testing PE32 VIH pin level [vih_tb]
Testing VIH DACs
Testing VIH level accuracy
Testing VIH apg level DAC select path
Testing VIH offset level accuracy
Testing PE32 VIL pin level [vil_tb]
Testing VIL DACs
Testing VIL level accuracy
Testing VIL apg level DAC select path
Testing VIL offset level accuracy
Testing PE32 VTT pin level [vtt_tb]
Testing VTT DACs
Testing VTT level accuracy
Testing PE32 VZ pin level [vz_tb]
Testing VZ level accuracy
Testing PE32 VOH pin level [voh_tb]
Testing VOH DACs
Testing VOH level accuracy
Testing PE32 VOL pin level [vol_tb]
Testing VOL DACs
Testing VOL level accuracy
Testing PE32 PE output impedance [pe_rout_tb]
Testing DP PMU voltage clamps [pmu_vclamp_tb]
Testing DP PMU current limit [pmu_ilimit_tb]
Testing DP DPS switches [dps_switch_tb]
Testing DP DPS current share [dps_share_tb]
Testing DP DPS sense resistor bypass diodes [dps_diode_tb]
Testing DP DPS compensation capacitors [dps_cap_tb]
Testing DP DPS leakage current [dps_leakage_tb]
Testing DP PMU compensation capacitors [pmu_cap_tb]
active dut = 0
Testing DP DPS current capability [dps_imin_tb]
Testing DP HV voltage force [hv_vf_tb]
Testing HV DACs
Testing HV level accuracy
Testing DP HV leakage current [hv_leakage_tb]
Testing DP HV current measure [hv_imeas_tb]
Testing PE Verniers [vern_check_tb]
Testing strobe modes [pe_strobe_mode_tb]
Testing PE32 XYAddr Pin Scramble [pe_ps_xy_tb]
Testing X Address bits
X Address 50.0MHz Test (20 ns)
Testing Y Address bits
Y Address 50.0MHz Test (20 ns)
Testing PE32 Data Pin Scramble [pe_ps_data_tb]
Testing Data bits
Data Bits 50.0MHz Test (20 ns)
Testing Data Strobes
Data Strobes 20.0MHz Test (50 ns)
Testing PE32 Chip Select Pin Scramble [pe_ps_cs_tb]
Testing Chip Selects
Chip Selects 50.0MHz Test (20 ns)
Testing Chip Select Strobes
Chip Select Strobes 20.0MHz Test (50 ns)
Testing PE32 Force Pin Scramble [pe_ps_force_tb]
Testing Drive L/H/Z
Drive Low 50.0MHz Test (20 ns)
Drive High 50.0MHz Test (20 ns)
Tri-State 50.0MHz Test (20 ns)
Testing Strobe L/H/V/M
Strobe Low 20.0MHz Test (50 ns)
Strobe High 20.0MHz Test (50 ns)
Strobe Valid 20.0MHz Test (50 ns)
Strobe Mid 20.0MHz Test (50 ns)
Testing PE32 XYAddr Pin Scramble [pe_ps_xy_ddr_tb]
Testing X Address bits
X Address 50.0MHz Test (20 ns)
Testing Y Address bits
Y Address 50.0MHz Test (20 ns)
Testing PE32 Data Pin Scramble [pe_ps_data_ddr_tb]
Testing Data bits
Data Bits 50.0MHz Test (20 ns)
Testing Data Strobes
Data Strobes 20.0MHz Test (50 ns)
Testing PE32 Chip Select Pin Scramble [pe_ps_cs_ddr_tb]
Testing Chip Selects
Chip Selects 50.0MHz Test (20 ns)
Testing Chip Select Strobes
Chip Select Strobes 20.0MHz Test (50 ns)
Testing PE32 Force Pin Scramble [pe_ps_force_ddr_tb]
Testing Drive L/H/Z
Drive Low 50.0MHz Test (20 ns)
Drive High 50.0MHz Test (20 ns)
Tri-State 50.0MHz Test (20 ns)
Testing Strobe L/H/V/M
Strobe Low 20.0MHz Test (50 ns)
Strobe High 20.0MHz Test (50 ns)
Strobe Valid 20.0MHz Test (50 ns)
Strobe Mid 20.0MHz Test (50 ns)
Testing PE32 Timing Generators [pe_tg_format_tb]
Testing NRZ Format 5.0MHz Test (200 ns) with Edge Strobes
Testing NRZ Format 5.0MHz Test (200 ns) with Window Strobes
Testing RTO Format 5.0MHz Test (200 ns) with Edge Strobes
Testing RTO Format 5.0MHz Test (200 ns) with Window Strobes
Testing RTZ Format 5.0MHz Test (200 ns) with Edge Strobes
Testing RTZ Format 5.0MHz Test (200 ns) with Window Strobes
Testing PE32 Timing Generators [pe_tg_dclk_format_tb]
Testing DCLKPOS Format 5.0MHz Test (200 ns) with Edge Strobes
Testing DCLKPOS Format 5.0MHz Test (200 ns) with Window Strobes
Testing DCLKNEG Format 5.0MHz Test (200 ns) with Edge Strobes
Testing DCLKNEG Format 5.0MHz Test (200 ns) with Window Strobes
Testing PE32 Timing Generators [pe_tg_mux_mode_tb]
Testing MUX Mode 5.0MHz Test (200 ns) with Edge Strobes
Testing MUX Mode 5.0MHz Test (200 ns) with Window Strobes
vmc_fifo_loop_branching_tb skipped - no LVM DIMMs present
vmc_ram_loop_branching_tb skipped - no LVM DIMMs present
lvm_subroutines_tb skipped - no LVM DIMMs present
lvm_subroutines_ddr_tb skipped - no LVM DIMMs present
scan_tb skipped - no LVM DIMMs present
scan_ddr_tb skipped - no LVM DIMMs present
Testing HSB sec. connections [apg_sec_tb].
active dut = 0
active dut = 1
Testing ECR [ecr1_tb]
Testing first 36 ECR data inputs with 18X, 0Y
Testing ECR0 first 36 error lines
Testing ECR1 first 36 error lines
Testing ECR [ecr2_tb]
Testing last 36 ECR data inputs with 18X, 0Y
Testing ECR0 last 36 error lines
Testing ECR1 last 36 error lines
Testing ECR [ecr3_tb]
Testing ECR address inputs with 18X, 8Y and full speed configuration
Testing ECR0 addressing
ECR0 first row
ECR0 second row
ECR0 third row
ECR0 last row
ECR0 diagonal
Testing ECR1 addressing
ECR1 first row
ECR1 second row
ECR1 third row
ECR1 last row
ECR1 diagonal
Testing ECR [ecr4_tb]
Testing ECR address inputs with 10X, 16Y and full speed configuration
Testing ECR0 addressing
ECR0 first column
ECR0 second column
ECR0 third column
ECR0 last column
ECR0 diagonal
Testing ECR1 addressing
ECR1 first column
ECR1 second column
ECR1 third column
ECR1 last column
ECR1 diagonal
Testing ECR [ecr5_tb]
Testing ECR clear with full speed configuration, 18X, 8Y
Testing ECR0 clear
Testing ECR1 clear
Testing ECR [dbm1_tb]
Testing DBM read widths with minimum speed configuration, 18X, 9Y
Testing ECR [dbm2_tb]
Testing DBM read speeds with 36 bit configuration, 18X, 6Y
Testing ECR [dbm3_tb]
Testing DBM write widths with minimum speed configuration, 18X, 9Y
Testing ECR [dbm4_tb]
Testing DBM write speeds with 36 bit configuration, 18X, 6Y
Testing ECR [dbm5_tb]
Testing DBM write to ECR capture with full speed configuration, 18X, 6Y
Testing DBM capture to ECR0
DBM to ECR0 first row
DBM to ECR0 second row
DBM to ECR0 third row
DBM to ECR0 last row
DBM to ECR0 diagonal
Testing CPUI in multiple sites per controller [multisite_cpui_tb]
Testing 2 Sites-per-Controller
Skipping - This site is not used in a 2 SPC configuration
Testing 3 Sites-per-Controller
Skipping - This site is not used in a 3 SPC configuration
Testing 4 Sites-per-Controller
Skipping - This site is not used in a 4 SPC configuration
Testing 5 Sites-per-Controller
multisite_cpui_tb PASSED.
Testing APG in multiple sites per controller [multisite_apg_tb]
Testing 2 Sites-per-Controller
Skipping - This site is not used in a 2 SPC configuration
Testing 3 Sites-per-Controller
Skipping - This site is not used in a 3 SPC configuration
Testing 4 Sites-per-Controller
Skipping - This site is not used in a 4 SPC configuration
Testing 5 Sites-per-Controller
multisite_apg_tb PASSED.
SystemDiag summary [diag_summary_tb]
Pass number : 1
Time for this pass : 00:08:58
Total time : 00:09:06
Final Bin: fail_bin
Done: 07/17/14 17:23:09
TestDone...bin = pass_bin.
NEXTEST/TERADYNE Magnum SSVは、大規模な集積回路の機能テスト用に設計された自動テストツールです。これは、最終的なテストアプリケーションに最大のスループットと精度を必要とするテストエンジニアに強力なソリューションを提供します。装置は8つまでの高度のテストカードを支えることができる非常に平行なテスターのシャーシから成っています。NEXTEST Magnum SSV制御ソフトウェアは、テストプロファイリング、データ分析、結果ストレージ、およびスクリプティング機能を備えています。TERADYNE Magnum SSVテストスイートには、アナログおよびデジタルパターンテスト、DC特性評価、パルスキャプチャと生成、シリアルデータトランザクション、ランダムなテスト生成などの豊富なテスト機能が含まれています。強化されたパターンジェネレータは、速度と柔軟性のために構築されており、テスト可能なクロック速度は最大500MHzで、Design-For-Test AddressingおよびACまたはDCテストをサポートしています。洗練された結果分析ツールは、テスト結果の詳細なレビューを可能にし、包括的な結果ストレージ機能は効率的な検索とトレーサビリティを提供します。Magnum SSVの高度なオートメーション機能は、バリアント制御、プログラム生成、スクリプトのカスタマイズなど、幅広いカスタマイズオプションをサポートします。既存のATEピンエレクトロニクス、テストプラン、外部アナライザ、およびATEラックとの統合は、システム独自のユニット制御および通信アダプタを活用することで可能です。複数のハードウェアプラットフォームと幅広いオペレーティングシステムをサポートするNEXTEST/TERADYNE Magnum SSVは、迅速で信頼性の高い最終テストに最適なプラットフォームです。NEXTEST Magnum SSVマシンは、密閉されたエンクロージャ、スケールされた電力供給、および包括的な負荷保護を備えた、最高のパフォーマンスと安全性を目指して設計されています。堅牢な設計により、過酷な環境での動作に適しており、産業環境での信頼性の高い動作を保証します。さらに、変更されたテスト要件を満たすために簡単にアップグレードできます。全体として、TERADYNE Magnum SSVは、最高の精度とスループットを目指して設計された高度なモジュラーテストツールです。強力なテストスイート、統合されたオートメーションツール、堅牢な設計により、最も要求の厳しい機能テストアプリケーションに最適なソリューションです。
まだレビューはありません